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TSMC is developing a new chip packaging technology called CoPoS, or Chip-on-Panel-on-Structure, according to sources familiar with the project. The company plans to begin mass production of chips using CoPoS by the end of 2028. This technology uses a glass material as a temporary carrier and as part of the final substrate, forming a three-layer sandwich structure.
CoPoS stands for Chip-on-Panel-on-Structure. The process involves using glass as a temporary carrier during manufacturing. This glass also becomes part of the final chip substrate. The three-layer sandwich structure is designed to improve both performance and manufacturing efficiency.
TSMC expects CoPoS to reduce manufacturing costs while enhancing chip performance. The technology is aimed at meeting the demands of AI and high-performance computing chips, where efficiency and speed are critical.
Nvidia's Feynman AI chipset will be the first to use the CoPoS packaging technology. This move highlights the focus on AI and high-performance computing as primary markets for the new technology. By adopting CoPoS, Nvidia aims to leverage improved performance and cost benefits for its next-generation AI hardware.
If CoPoS proves successful, it could strengthen TSMC's position as a leading chip manufacturer. The adoption of this technology may prompt competitors to develop alternative packaging solutions to keep pace with TSMC's advancements.
TSMC's commitment to mass production by 2028 signals a significant shift in chip packaging methods. The company aims to maintain its competitive edge in the global semiconductor industry by introducing innovative manufacturing techniques like CoPoS.
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